1. Field of the Invention
This invention relates to a multiport memory device, and more particularly to a multiport memory device featuring an improved method of extracting data from the latch circuitry.
2. Description of the Related Art
Recently, there have been strong demands in the field of microprocessors toward higher performance. One way to meet such demands is to speed up calculation by parallel execution. To execute parallel operation at high cost performance requires multiport memory devices.
Multiport memory devices allow a plurality of read ports to read the same or different words of data in parallel, and a plurality of write ports to write the same or different words of data simultaneously.
A read/write single-port static RAM memory cell is shown in FIG. 1, where reference characters G1 and G2 indicate transfer gates, respectively. To read data from and write data into a latch circuit 10, a word line WL is first selected, transfer gate transistors G1 and G2 are turned on and off to electrically connect the latch circuit to bit lines BTL and BTL, thereby transferring the data in the latch circuit 10 to the bit lines BTL and BTL. A memory cell of multiport design is shown in FIG. 2 as an extension of this technology. As shown here, a plurality of transfer gate transistors G1 to G6 are each connected to two inverter outputs constituting the latch circuit 10. For reading/writing of data, like the above single-port memory cell, word lines W1 to W3 are selected to turn on and off G1 to G6, thereby electrically connecting the latch circuit 10 to bit lines B1 to B3, and B1 to B3.
In the multiport memory, however, when a plurality of ports read the data from a cell at the same time, the potential at the cell becomes unstable seriously. For example, with the potential at node J1 at the high level and the potential of bit lines B1 to B3 at the low level in FIG. 2, when transfer gate transistors G1 to G3 are all turned on by simultaneous selection of word lines W1 to W3, the potential at node J1 drops. A drop in the potential at node J1 can reverse the data in the cell.
As mentioned above, in the multiport memory cell, when data is read out by a plurality of ports, there is a high possibility that the data in the latch circuit may be destroyed.